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Analogue design by molecular modeling is becoming an important strategy in the development of new antiretroviral drugs. An example of the design of new nucleoside reverse transcriptase inhibitors is provided by the work of Mitsuji Akashi, providing motivation for improving the activity of AZT, 3TC and DDI. In several cases, several different antiretroviral compounds that seem to have some common features are actually structurally unrelated molecules that achieve activity through distinct mechanisms. In this case, the design of novel dual inhibitors, combining an attachment inhibitor with a viral integrase strand transfer inhibitor, is an example of a new strategy being exploited. An example of a novel attachment inhibitor is DMP-266, which acts via an unconventional mode of action and can be docked in the cavity defined by the CN/COG tripeptide of the viral gp41 structure. This cavity is currently being explored for new drug design. This review provides a description of novel compounds in current use and future design.Q:

Expressing ease of use as a good reason?

Is it considered polite for a driver to say to a passenger that he is or she is an “easy person to drive”, for example during a recent one-hour drive?
For example, to reply to a passenger who asks “Is it easy to drive this car?”, thus:

Yes, it’s easy.

Why is that considered polite?
Why is it considered rude to reply to an expression of ease of use (of something, as in the question’s example), thus?

Well, it’s not easy to drive this car.


In the US I

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1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device and a semiconductor device fabricated by the method and, more particularly, to an electrically erasable programmable read only memory (E.sup.2 PROM).
2. Description of the Prior Art
As shown in FIG. 1, a conventional E.sup.2 PROM is manufactured by forming an N-diffusion layer 11 which functions as a drain region, a P-diffusion layer 12 which functions as a source region and an N.sup.+ -diffusion layer 13 which functions as a floating gate in a P-type silicon substrate 10 by an ordinary CMOS process. The fabrication steps are explained below.
(1) A P-type well region 2 is formed in a prescribed region of the P-type silicon substrate 10.
(2) An N-well region 3 is formed in the N-type silicon substrate 10 by an ion implanting process and a thermal process.
(3) N.sup.+ – and P-diffusion layers 11, 12, 13 are formed in the prescribed region.
(4) A device isolation region (field oxide film) 4 is selectively formed by an ordinary selective oxidation process.
In such a conventional E.sup.2 PROM, there is the problem that high-resistance poly-crystalline silicon is used for the source and drain regions, which can result in an increase in the memory area.
The conventional E.sup.2 PROM is manufactured according to the CMOS

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